The present invention relates to a gray code decoding circuit of a hard disk drive and more particularly to a gray code decoding circuit which can decode a gray code recorded in a servo pattern area of a disk.
Generally, a disk of a hard disk drive having a high rotational speed, large capacitance, and high density maintains a constant rotational speed. The disk generally contains a servo pattern 1 where all kinds of information capable of effectively controlling a head position is recorded. As shown in FIG. 1, the servo pattern 1 generally includes a write/read recovery area 2, a pattern area 3 in which a specific pattern or a direct current gap is recorded, an index mark IM area 4, a gray code GC area 5, a servo track mode STM area 6, and a post amble data PAD area 7.
The write/read recovery area 2 is formed, considering the transition time required for the hard disk drive to change from a write mode to a read mode, to prevent errors caused by transition noise. These errors can include, for example, barkhausen noise generated by a magnetic flux change applied to the head. In the pattern area 3, the direct current gap or the specific pattern is recorded for synchronizing a detection timing of the servo pattern with a system clock. The pattern area 3 is also referred to as an address mark AM area. On the index mark IM area 4, index information of the disk is recorded. On the gray code GC area 5, identification ID of the track of the disk is recorded as a gray code GC. On the servo track mode STM area 6, a burst signal used for controlling a track following is recorded. A frequency of the servo pattern shown in FIG. 1 is approximately 4 MHz.
Moreover, the gray code used for recording identification of track within the gray code GC area 5 is comprised of 12 bits (in the configuration of 4096 cylinder). The reason why the gray code is used for discriminating the identification of the track is in that the gray code can be easily recognized as being converted by one bit when the head moves track by track, compared to the conversation of binary or decimal codes.
The gray code recorded on the disk, as shown in FIG. 1, is divided into gray synchronous signals S.sub.11, . . . S.sub.0 ! and gray data D.sub.11, . . . D.sub.0 !.
Therefore, the length of the gray code area for the servo pattern is obtained by the following equations and equalities.
SCLK (system clock)=32 MHz=31.25 nsec=1 T PA1 1 cell=4 T=125 nsec PA1 1 di-pulse=2 cell=250 nsec PA1 L=12 gray synchronous signal+12 gray data
Consequently, the length of gray code area, L, is determined as follows:
=24 di-pulse=48 cell PA2 =48.times.125 nsec=6 msec
FIG. 2 is a diagram illustrating a gray code decoding circuit of a conventional hard disk drive. FIG. 3 is a timing diagram illustrating a conventional gray code decoding operation.
An operation of a conventional gray code decoding circuit of FIG. 2 will be herein discussed with reference to FIG. 3.
When a disk 12 rotates by the operation of a spindle motor (not shown), a head 14 reads the signal stored within the servo area shown in FIG. 1 from the disk 12 and then transmits the read signal to a read/write channel part 16. The signal may be a head pickup signal waveform as illustrated in FIG. 3,
The read/write channel part 16 is typically comprised of a peak detector, a hysteresis comparator, and a one-shot data generator. The read/write channel part 16 converts the read signal into digitalized encoded read data ("ERD") and outputs the ERD to a pattern detector 18.
The pattern detector 18 makes the system clock SCLK and the servo pattern synchronous to each other, generates a reference pulse RP indicating the start of the servo area, as shown in FIG. 3, and outputs the reference pulse RP to a gray code decoder 20.
Then, the gray code decoder 20 decodes the continuously received ERD into gray data GD in response to the reference pulse RP, as shown in FIG. 3. Furthermore, the gray code decoder 20 counts a data pulse received following the reference pulse RP to generate a gray synchronous window GSW and a gray data window GDW, as shown in FIG. 3. Thereafter, in accordance with the gray synchronous window GSW and the gray data window GDW, the gray code decoder 20 decodes the gray data GD into a gray code GC and then outputs the gray code GC to the input terminal of a gray-binary converter 22.
As shown in FIG. 2, the gray-binary converter 22 then converts the gray code GC to a binary code B and outputs the binary code B to a microprocessing unit MPU 24. At this time, the binary code is binary data providing identification information for a track.
However, in a hard disk drive operating at a high speed, the conventional gray code decoding circuit as set forth above cannot accurately access the gray code because of the following problems, thereby making the reliability thereof seriously unstable.
Firstly, the maximum seek time taken until the head arrives at its destination depends upon the length of the gray code, which can be an important problem. In other words, the time required for the head to read and pass the gray code of the servo pattern previously recorded on the disk needs to be reduced in order to have a rapid seek time.
Secondly, the reliability of the gray code detector can be lowered by a bit shift of the ERD. The gray code decoder counts the data pulse received following the reference pulse RP and generates the gray synchronous window GSW and the gray data window GDW. When a bit shift of the ERD is increased due to the timing shift generated by the synchronism between the system clock and servo pattern and a jitter of a spindle motor, the reliability of the gray code decoder is lowered.